ASE Expands PowerSiP™ Platform for Next — Generation AI Power Delivery

For best results when printing this announcement, please click on link below: ASE Expands PowerSiP™ Platform for Next-Generation AI Power Delivery Vertically integrated 3D SiP modules shorten high-current transmissions path, reducing parasitic routing losses by 50% or more to enhance system efficiency Advanced Semiconductor Engineering, Inc. , Ltd.

(NYSE: ASX, TAIEX: 3711) and a leading provider of semiconductor assembly and test services, today announced the expansion of its PowerSiP™ platform with a 3D System-in-Package (SiP) solution designed to enable vertically integrated voltage regulator modules (VRMs) for higher system efficiency in AI data center and high-performance computing applications. Available now, the solution combines qualified assembly technologies and a sub-module toolbox to support miniaturized, highly integrated, and thin VRMs for vertical board-to-chip power delivery.

By bringing voltage regulation closer to the processor, the vertical architecture can cut parasitic routing losses by 50% or more, helping improve overall system efficiency as AI compute power requirements continue to rise. As AI processors continue to scale in performance, their energy requirements are increasing significantly, making efficient power delivery a critical system-level challenge. Today’s high-performance AI SoCs can exceed kilowatt-level power and require peak currents greater than 1,000 amps at sub-volt levels.

At these currents, traditional lateral architectures can introduce significant routing losses as electricity travels across the PCB, through package substrates and interconnects before reaching the processor. Reducing the distance between voltage regulation and the processor is therefore becoming increasingly important to minimize losses and improve overall system efficiency.

ASE’s PowerSiP™ vertical integration toolbox includes double-sided connected capacitors sandwiched between coreless substrates; substrate-less, solder-free cap array modules with exposed terminals for embedded substrate or PCB solutions; high-aspect-ratio 4:1 copper pin integration for lower packaging impedance; and high-density active and passive component integration using single- or double-sided molding. Together, these capabilities address the density and thickness constraints associated with placing voltage regulation on the back side of the PCB in space-constrained compute trays.

“Power efficiency is becoming a defining challenge for next-generation AI systems,” said Dr. Harrison Chang, Vice President of Corporate Research and Development at ASE. ” “AI systems are placing unprecedented demands on board-to-chip power delivery, making the final stage of voltage regulation increasingly important,” said Dr. C.

P. Hung, Vice President of Corporate Research and Development at ASE. ” “As AI infrastructure evolves toward increasingly heterogeneous and modular compute architectures, system-level power efficiency will become even more critical. The expansion of PowerSiP™ reflects ASE’s focus on packaging innovation that addresses broader system-level power challenges,” said Yin Chang, Executive Vice President at ASE.

” Simultaneously, ASE will participate at OCP 2026 in San Jose, from October 13 to October 15, where Corporate Vice President Dr. ” Supporting resources For more, please visit: Follow us on our LinkedIn page for targeted updates and announcements: @aseglobal Follow us on X: @aseglobal About ASE, Inc. ASE, Inc. is the leading global provider of semiconductor manufacturing services in assembly and test.

Alongside a broad portfolio of established assembly and test technologies, ASE is also delivering innovative VIPack™, advanced packaging, and system-in-package solutions to meet growth momentum across a broad range of end markets, including AI, Automotive, 5G, High-Performance Computing, and more. com or follow us on LinkedIn & X: @aseglobal. com)