Faraday Technology Debuts 14nm MIPI C/D Combo PHY IP
The silicon-proven IP runs on UMC 14nm FinFET and supports C-PHY v2.0 up to 3.0 Gsps/trio and D-PHY v2.5 up to 4.5 Gbps/lane, with more than 30% die-area reduction through shared resources.
The silicon-proven IP runs on UMC 14nm FinFET and supports C-PHY v2.0 up to 3.0 Gsps/trio and D-PHY v2.5 up to 4.5 Gbps/lane, with more than 30% die-area reduction through shared resources.